Sheet 1 of' 1M Biurets
Division 8- — Lfcacoln. Laboratory
SAft3sacixitwtt3 Institute of Technology
Lexington ts, M&s&schusetts
SUBJECT: A TSJWatSCOBlSaBD VAKOkHLl USUI' OMIT
Qromp 63 Staff
September 12, 1957
Abstracts Thisfpraasistorised variable delay unit convert a a neigati?®
pole* into a 3 volt negative levsl whosa width Is adjustable over a
i«t|g# from 0*3 iderfsseGnds to 2.$ second** Greater widths may be
f^tajabd "by. adding capacitance i ext.»ra«Hjr» "Shen loaded with 100 ohm
Wm-wtopxt level is -2„9 volta,-£*H tin* is 0.09 microseconds, and ■
T$&» tin® is 0.03 microseconds a A coa^pensating circuit for voltage
di4ft> is included which maintains the delay width .ocaastant within 1a$$
ttattt '0»3 p®r cent for a 10 per ceat variation in &ay supply voltage*
«£Ltt*r is below 0,1 per cent.
later, S» (Group 2k)
/tttt, s, x*
. $&(%!&£, J«ls»
Kielnrcsk, L. (10 )
us flrti: t> k* =oi tews, «ws->»i
«* *t &}?«» *rttfi»* ttS#^*W
Qlsaa, K»H. ' J ;
Peterson, H.P. ;
Pugsley, J* -
8a.r*ll f a.
to Rscms jjb8s?8*cts obhiv
TABLE OJ? g;_0_'C_T_5JT_T_g
CIRGJITKr AMD OPEMTiar ......... 3
PEKFOfMANCE ............... 7
SPECIFXCATICMS AND RANGE* ..••••.. 8
_ ' , ,«•« t - ./ , , . 'i „ " .■ vi.** , > •» •-'<• „f. t .. ! ''V ■;
- . • ?. - It .»-• . i* ••,*"; V;*' rt»l ,t'* ' :• *> ■ „>f- "V* .
high, Tnls unit will! supply ft 100 ohm resistive load with 4 -11
bjvel whose fall ti«e Is 8 09 microseconds and whoaset rtee tiiis i,i
microseconds* Jitter is kept down to less than 0*1 per $snfc* TI
pulse width may be varied continuously over the entire rn,r *' -<- ?
seconds to 2«5 seconds with 5' coarse positions* longer daisy a m
obtained by adding capacitance externally at the terminals pro"cii„...„ _..
output palse width is affected only slightly by sapply voitag© v&riatior.s,
@»g# for a 10 per cent change in any 'supply voltage, the widt.ii change©
by less than 0.3 pW cent*
As a first attenpt in solving the problem of designing a
variable delay unit, a monostable multivibrator was investigated. The
emitter coupled type was eliminated because of its undesirable output
pulse level, i.e.^ the output swing is not from ground level to -3 Toits*
The collector coupled raonoetable multivibrator showed more promise.
However, the following difficulties were encountered. Referring to Figure
1, note that the delay time is directly proportional to the product of ILCi
6M -5 216 2
However, the maximum value of 10. is limited because the d~c base currant
for transistor Q2 must flow through El, If we desire a lonf delay tire
a® will therefor© find it necessary to, Increase the value of C s This
brings us to a second difficulty, namely, that the recovery time (which
is proportional to th© product R-C), becomes excessive. These problems
were overcome by placing an emitter-fello«ier between R2 and C as well as
between Rl and the base of translator Q2, This circuit however introduced
too much delay time during the regeneration period (transition period)
which resulted in a slower output waveform than could be acceptable,
It was decided that a monostable multivibrator which depends
upon internal delay for its proper functioning would not be suitable, and
so a circuit using external delay was investigated* As shown in Figure 2
the negative input pulse Bets the flip -flop in the state, and, after a
.time interval, a signal fed back from the BC timing circuit sets the flip-
flap, in. the 1 state (by definition^ th© side which 'is set supplies a
_ r-c : set
JT J TIMINO " | €lf
i — - - -™i
FLIP-FLOP WiTH EXTERNAL DELAY
The set one pulse coming from the timing circuit was too slow to give a
suitable trailing edge to the output waveform, and so an emitter coupled
bistable «ltivibrator # ale© known as & Schmitt circuit , was added, as
shown dotted in figure 2* This provided an extremely fast set one pulse*
A Sehndtt circuit reiponds only when the input signal exceeds a sdniimw,
amplitude, which is known as the triggering l*?v*l, l\ Ik *, :»,"-"-< ,: ■ ■ < ,
is sansitlvs to supply voltage, drifts,, m i«? ite timing cirri. V" ,■:>:;
therefore In an attempt to compensate for such drift,-, b«< fi circuits
wore Ri.pp.Meci fr-m the same voltage nourcee. This rrontly redu^d the
sensitivity of the delay width' to supply voltage drifts. Basically this
is the form of the final circuit. Further improvers are described
CIRCUITRY AND OPERATION !
A block diagram and a circuit schematic of the variable delay
unit are shown in Figures 3 and 6, respectively. In brief, the operation
, of the circuit is as follows. A negative input pulse is applied to the
input trigger stage. This triggers the flip-flop and sends the output
from ground level to the -3y level. At the same time this initiates a
timing circuit, which compensates for supply voltage drifts, and allows
a time interval to pass during which the output is held at the -3v level.
At the end of this time interval the Schmitt circuit is triggered which '
in turn triggers the flip-flop. The flip-flop then goes through a second
transition returning the output to the ground level. The width of thla
output pulse is thereby determined by the setting of R and C only.
SETQ SET I
BLOCK DIAGRAM, VARIABLE DELAY UNIT
In detail, the circuit operation may be described as follows.
In the quiescent condition, assume that the flip-flop is in the 1 state
(this is verified further on), setting the output at ground potential.
When a negative pulse arrives at the Input terminal, the collector of Ql
and of Q3 are both pulled toward ground, from -3 volts, Tr-is starts the
iaTUieition of the flip-flop which thbaxIz in u--s coU^^r , ;; f q 3 rw*^,-.-,
at ground potential and the collector of QU, as well as the output terminal
btiiftlnp to the -3 level* The output, pulse has now started*
The base of Q6 is now pulled to ground which cuts off this
transistor* The voltage across C up until this time had been volts due
to tne claiming action of Q6. Now that Q6 has been cut off the potential
at lt« collector begtna to riee from 3 volte toward * 10 volte. The
iata of rise is Inversely proportional to the product RC» The emitter-
follower, W?i follows directly with the rising voltage at its base, Q6
and Q? comprise the timing circuit.
The signal is now fed into a drift compensating circuit which
functions as follows. The assumption is made that transistor Q8 does not
conduct until its emitter potential equals or exceeds the potential of
its base, at which time Q8 with its associated load resistor act as a
standard inverter type circuit. In Figure k is shown a plot of the voltage
at the emitter of Q8 versus time.
8 £ VOLTS
~ - TRI83ER LEVEL
-••• --■ -TRIGGER LEVEL f
TRiOOER LEVEL ADJUSTMENT
Here the aesusption is made that this waveshape is linear, whereas it is
known that this is an exponentially rising wavef orsi. This assumption is
valid since we are dealing only with a snail portion of this waveform at
its beginning where it is nearly linear. In this Figure, E volts repre-
sent the absolute difference between the *10 and -3 supply voltages,,
line AB represents the waveshape for a *10 supply voltage of value *10
volts. Assaying, for the moasnt, that the base voltage is fixed at a
level which *»- shall call trigger level 1, it is seen that at time tl> the
inverter will ■tart to conduct. Assuae now that the supply voltage drops
by an awxmt delta E as shown in Figure k at point C. line AC now repre-
sent* the msvfttape at the emitter of Q8. The intersection of this line
and trigger level 1, occurs at a tine t2 which is greater than the
desired tise tl« One way to compensate for this change in time is to
e&aage the trigger level from trigger level 1 to trigger level 2 which
£!!Ur4fcMi.«tM»-tlM' intersection to occur at the desired time, tl. B^-
triangles it is seen that,
level 2 E - AE
level 1 " ~E —
trigger level 2 - ft g a * trigger level 1
This gives us the valne of the *m desired trigger level. One obvious way
te ttt tale aev ferlgge? level is U put the base of Q8 at this new level*
This my be i eutcsgatleally by connecting $9 as shown in Figure
5. Frem ear erigSaal assumption we have defined the base voltage to be
the trigger level. For the eeaditiea where the *30 supply voltage is"
equal to #10 volts, the trigger level is equal to
trigger level 1
If now- the supply voltage changes by a quantity - m the new trigger level
trigger level 2 « jj-STW f S " ^"J
m^.r\ / -
U-i- SO VOLT4
D*IFT QOMNNtATION FOR 4 J© v A*l® -l y SULLIES
Combining thst* two aquation®, we see that
trigger level 2 . pLjiLl trigger level 1
By collaring this trigper level 2 to the desired trigger level 2 ae
determined from Figure k, we see that they are identical, and have thereby
compensated for the change in the + 10 supply voltage. By superposition,
a change in the -3 volt supply will be, compensated for in the identical
manner. Note that the values of Rl and R2 do not enter into the final
equations, and may therefore drift without consequence. They have beer,
chosen to fall within the operating range of Q8.
The collector of Q8 will start rising at a time determined only
by the setting of R and C and not dependent upon the supply voltage level.
The inverting action through Q8 also has associated with it a large gain
which effectively amplifies the slope of the waveform at its emitter.
This signal is then raised roughly 3. 1/2 volts through the Zener diode
and appears at the base of Q9 which is the input to' the Schmitt circuit.
The base voltage of Q9 is held clamped at a potential determined
by the constants of the Schmitt circuit, the Zener diode, and the 5,6 H
resistor. Therefore the collector of Q8 is clamped at a potential'
roughly 3»5 volts negative of this, When the collector of Q8 begins to
rise, the base of 09 rises with it at higher level. The Sehtaitt eiwmit
is set to trigger at a voltage roughly 1 rolt positive of its elated
voltage, When the Sehs&tt circuit trigger e, the collector of C&0 sharply
rises fro»;ab©ut -4»8 volts to a level slightly above ground, which out®
off Qg« This triggers the flip-flop and forces a transition to take
place „ The output at 05 now swings from its »3v level to the ground level
which thereby terminates the output pulse The racoTery tine has been
aiairaiaed by allowing C to recharge through the collector current of Q6«
Yariatioas in the -I5v supply alter the delay tins by affecting
the quiescent base voltage of Q9» However* by adding the 121 resistor
from this supply to the base of Q8, a correcting signal is generated
which compensates for such drifts.
The assumption smde in the second paragraph of this section nay
now be verlf led. If the flip-flop were to remain in the G state, the
tisdsig circuit would begin functioning (sine© Q6 would be cut off } f «ad
this would be fed through to the- Scha&tt circuit , which would •wrtoally
trigger * One® triggered^ the collector of Q1D juaps shorn ground
potential* and this is fed to the base ©f 02 which anst therefor® a6«p
««iuetlng* If 02 is sot conducting* the flip-flop met swtteh to it® 1
f igure 7 shows photographs of the vavafemw at eritlcitl polzri*
ift tte oiiual*. The delay ti*» was arbitrarily set at W aieroseeoxtds*
late %h» llatar rtm in veltafa at the base ©f Q?* and tba ' sjs>lifi*d .slop*
«f this rifts at the inprfc to the 8Uudtt circuit® lota •!*» feat tha
'qpiaoawt lw»X at whish the output signal settles is a fw tooths of a
volt slssm gammd* fids allewts dir»@t wapling to a txwaalstor base*
without &£M$m positive H&i 8 It nay aloo be seen that the 100 oh& U&A
■hardly alters th# output swing,
'F&gax* 6 ghewa th* varlAtlon la output palm width as a function
of the aapply voltage** far * puis* width of 100 s&eroaeeosds* lfot« that
£ er * # 10 per ©«et ehang* i» supply veltaca, tha pals® width rmmim
constant within- # 0»3 per east*
As is the practice with such circuits a number of margin check
plots were made which proved quite satisfactory, giving -aid® margins for
variations in the important parameters,
Further data in this respect may be found in Lincoln Laboratory
Computation Book Number 1307,
SPECIFICATIONS AND RANGE S
1„ Inputs Requires a negative pulse uhose jainiraum amplitude
is -1.5 volts and whose duration should be at least
20 per cent lass than that of the desired output
2. Output* (a) Minima delay times 0.3 microseconds,
(b) Maximal daisy timet 2.5 seconds.
Notet Longer delays nay be obtained by adding external
capacitance at the terminals provided.
(c) Fall time unloaded! 0,0$ microseconds
Rise tins unloadedt 0.03 microseconds
Pall time loaded with 100 ohmet 0.09 Micro-
Rise time loaded with 100 ohmst 0.03 micro-
(d) Output swing, unloadedt -3 volts
Output swing, loaded 100 ohmst - 2.9 volts.
3. Maximum pulse repetition frequency at minimum delay times
lu Jitter t 0.1 per cent
5» Supply voltages? ♦10, +10 MCV, -3, -1$. Notet This
circuit can also be changed for operation at -10 instead rf
-15 VOlt So
6* Serai -conductors requireds ? Philcc type L-5122 transistors,
3 Philco type L-513U transistors, 1 Texas Instrument type
60000 Zener diode .
- 7*5 pais*
- ll|0 |MM>C.
- 2S m*
- 90 3»*
- 2*$ sac,
Notes Whan adding external capacitance to obtain longer delays, pat a
1*7 oh» resistor in series with the capacitor to limit excessive
8« Polarity of Output gigaal g The circuit described in thl*
nets gives an output that is quiescently at ground pe^ettHag*-
and then drops to -3 volts for the duration of the pulse «
If desired, an output raay be obtained which nornaUy
supplies a ~3v level, and rises t© ground potential for tits
duration of the pulse* This may be aeeoBfjlished by feeding
the output into a clamped inverter (for low power applica-
tions) or into an inverier-easeode eoafcination (for higher
power applications) as is used in the TX«-2 eoapater
Figure 6, Dwg. Ho. B-83082
Figure 7, Dwg. A-63295
Figure 8, Dwg. A-8326S
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Memorandum 6H-J8Q.6, SI
Sheet l of 6 Sheet*
Division 6 — Lincoln Laboratory
Massachusetts Institute of Technology
Lexington 73, Massachusetts
A TRANSISTORIZED VARIABLE MKLAf WIT
Group 63 Staff
Jonathan R. Padiaan &*»*^&«~ K
January 20, 1958
Ab tract : The rmi^kble delay unit described in 6N-J216 baa beea slightly
aodif led for use in the TX-2 coaputer. Key points in the circuit are
brought out to pins on the plug. The unit amy be used in various vays
according to the pin connection* aade on the plug. The proper delay range
is also chosen by external pin connections. The Maxima output current is
15 aa. at -3 volte, and 6 aa. at ground. The delay unit synchroniser, the
delay unit auxiliary, and the variable delay coupling unit are described.
Baker, It. (Group 2*0
Best, R. L.
Cord s r asa, C.L.
Fadinaa, J.R. (3)
Our ley, B.N.
Peterson, I. P.
Raff el, J.
RSOUDBE OF (HOOP 63 STAFF
TO nCUTI ABSTRACTS OUT.
._ VJi? ^"J"*'". '"I "•" >"**"* *<* "*•"•' "• "H> It l« not M«i rxltmd
ft. "US', * S * Cdrlt / * wl **' D""*™** <* Def.**, M Iknfirt, li not inttrnM
Mr piAlk must. Firtiwr dintmiMtior or rtcrwhction h whole or in ptrt of th*
iflwtwul within tilts docurwrt shsll net tw imk without the ennts writtw aporovil
01 Lincoln Ufcorttor) (Publications Otfict).
2. Tin ! ■ ■■ narM In this
upiortX JtiMly ky tin Ocprtnim of ttH Ana,
Me D mh u i h ii I of On N*w, km) Uk Dt*rt-
MMt W tht Air Fsrot mlar Air Fan* Canbaet
Ne AF H (1I21-4M.
6M- 5016, SI 1.
The basic variable delay circuit has been slightly modif ied and
adapted for use in the IS -2 counter. The -15 rolt supply voltage has
beea changed to -10 volts, and much greater flexibility for use in TX-2
has beea achieved by bringing out certain key points in the circuit to
pias on the plug. There have also been some changes in circuit values
in order to achieve no*® reliable operation. The circuit, as it is used
in TX-2, is given in Figure 9. Figure 10 is a block schetsatlc. The
co^lete assembly and composite of the plug-in unit is given by D-8%175.
For normal operation, pin J is connected to pin D, and pin I is
connected to pin L. The proper capacitance is selected according to the
delay range desired. The fine delay is adjusted by means of the trimpot
which is a special wire-wound Bourns Tria-r made to have a radniwaa end
resistance of only 100 ohms. The recovery time is constant for any
given capacitance. The delays available and the proper in connection®
are given below.
0.5 ua ec «
The delay as a function of capacitance is given approximately by
.l%€<t<12C, where C is the capacitance in *&fd and t is the length of
delay in seconds. This holds only for t> .5 ^seconds.
For longer delays than are available from the capacitances in the
unit, added capacitance may 1»e connected between pin L and the -3 volt
supply. For example, a 4000 >*fd condenser will provide a delay
variable from 900 milliseconds to 5* seconds with a recovery time of
H00 milliseconds. A 22 oba resistor must be used in series with the
capacitance to limit the charging current if C is greater than 10 |tfd.
Slight variatioas in delay in any one range will be noticed from unit
6M- 5216, 81 2.
to unit, caused by the 20% capacitor tolerance. Sufficient overlap is
prorided to take care of this, but in general the capacitor should be
chosen eo a* not to use the very end of any one range.
For synchronised operation, pin J is not connected to pin D.
Instead, a gating circuit built fro* a P-5 unit is inserted as shown in
Figure 11. The output of the Schmidt circuit, obtained frosi pin J,
swings from ground to -3 volts. However, the -3 volt lerel is supplied
by a 820 ohm resistor to -3 rolts, which makes it necessary to use two
transistors in parallel in the P-5 unit. The output of the P-5 unit
will be a posit ire pulse from -k rolts to ground, which will occur on
the coincidence of a negative 2.5 volt «ymchroniaing pulse and a
ground level output from the Schmidt trigger of the delay unit. Thus
during synchronized operation, the delay time will equal the length of
the variable delay setting plus the time until the next synchronizing
pulse comes along.
In order for the delay unit to be controlled from the output of a
decoder, pin J is connected to pin D as usual and pin H is not connected
to pin L. Instead the auxiliary delay unit (Figure 12) is inserted.
Any or all of pins D, J, I, and T of the auxiliary unit are connected
to pin L of the variable delay unit. The length of delay will be
controlled by the settings of the variable resistors in the auxiliary
unit, by the decoded Inputs to the diodes of the auxiliary unit, and
by the capacitance range chosen.
The Input t. the delay unit at pin B may be a negative 2-5 volt
0.1 usee, pulse or a negative-going 3 volt level which is at least
20% shorter than the maximum desired delay time. The collectors of
other gated pulse Inputs may be connected at pin T as In the standard
two transistor gate to the "one" or "aero" input of a flip-flop. A
positive going level may be used to trigger the delay by forming a
negative pulse from it and triggering at pin B. A circuit which will
accomplish this is included in '-he variable delay coupling unit, to on
described be lew.
The output of the delay unit is normally at ground, and goes to
-3 volts during the delay. The maximum output current is 15 ma. at
-3 volts, and 6 ma. at ground. Thus the output will drive 10 inverter
bases, or 10 emitter-follower bases, or any combination of these two
not exceeding 15 ma. at -3 volte. The output may also be used to drive
the emitter of a single pulsed transistor.
It may be desired to have a delay which will last for a given tUmt
after the last of a series of pulses. This can be done by using two
variable delay units and the variable deity coupling unit. The circuit
schematic of this unit is given in Figure 13- The output of TD X is
connected to pin D o? the coupling unit, and the output of VDg i»
connected In pin J. YI^ !• triggered from the negative pulse obtained
from pin L of the coupling unit. Pin B of the coupling unit is
connected to pin L of VDg. The desired delay is obtained from pin V
of the coupling unit. It is a level which is normally at -3 volts,
and goes to ground for the length of the delay. The level goes to
ground at the first pula*, and stays at ground for a length of time
after the laet pulee equal to the length of the first delay plus the
length of the second delay. The maximum output current is 10 ma. at
-3 volts, and 6 ma. at ground. In adjusting the length of the delays,
TDi plus its recovery time must be less than VDg. In addition, TDi
must be greater than the recovery time of TD2. The minimum resolution
time of this circuit is equal to the length of TDx plus its recovery
Figure 9, Dwg. «o. SB-85602
Figure 10, Dwg. Jto. la-85^30
Figure 11, Dwg. «o. Sa-85603
Figure 12, Dwg. Io. aa-8560*
Figure 13, Dwg. Io. Sa-85605
CIRCUIT SCHEMATIC VARIABLE
DELAY UNI T
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